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Cypress Semiconductor Electronic Components Datasheet

CY7C1378C Datasheet

9-Mbit (256K x 32) Pipelined SRAM

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CY7C1378C
9-Mbit (256K x 32) Pipelined SRAM
with NoBL™ Architecture
Features
Functional Description[1]
• Pin-compatible and functionally equivalent to ZBT®
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 256K x 32 common I/O architecture
• Single 3.3V power supply (VDD)
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable (OE)
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
The CY7C1378C is a 3.3V, 256K x 32 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1378C is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.8 ns (250-MHz device)
Write operations are controlled by the four Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1378C (256K x 32)
A0, A1, A
MODE
CLK
C
CEN
www.DataSheet4U.com
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
BWC
BWD
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05687 Rev. *F
Revised September 14, 2006


Cypress Semiconductor Electronic Components Datasheet

CY7C1378C Datasheet

9-Mbit (256K x 32) Pipelined SRAM

No Preview Available !

Selection Guide
Maximum Access Time (tCO)
Maximum Operating Current (IDD)
Maximum CMOS Standby Current
Pin Configuration
250 MHz
2.8
250
40
200 MHz
3.2
220
40
100-Pin TQFP Pinout
CY7C1378C
166 MHz
3.5
180
40
Unit
ns
mA
mA
NC
BYTE C
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
www.DataSheet4U.com DQD
VDDQ
VSSQ
DQD
BYTE D
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1378C
80 NC
79 DQB
78 DQB
77 VDDQ
76 VSS
75
DQB
BYTE B
74 DQB
73 DQB
72 DQB
71 VSS
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58
DQA
BYTE A
57 DQA
56 DQA
55 VSS
54 VDDQ
53 DQA
52 DQA
51 NC
Document #: 38-05687 Rev. *F
Page 2 of 13


Part Number CY7C1378C
Description 9-Mbit (256K x 32) Pipelined SRAM
Maker Cypress Semiconductor
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CY7C1378C Datasheet PDF






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