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CY7C1354D Datasheet

9-Mbit (256K x 36) Pipelined SRAM

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CY7C1354D
9-Mbit (256K × 36) Pipelined SRAM with
NoBL™ Architecture
9-Mbit (256K × 36) Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible and functionally equivalent to ZBT
Supports 200 MHz bus operations with zero wait states
Available speed grade is 200 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
Single 3.3 V power supply (VDD)
3.3 V or 2.5 V I/O power supply (VDDQ)
Fast clock-to-output times
3.2 ns (for 200 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in non Pb-free 165-ball FBGA package
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
Logic Block Diagram – CY7C1354D
Functional Description
The CY7C1354D are 3.3 V, 256K × 36 synchronous pipelined
burst SRAM with No Bus Latency™ (NoBL logic, respectively.
They are designed to support unlimited true back-to-back
read/write operations with no wait states. The CY7C1354D are
equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature greatly improves the throughput
of data in systems that require frequent write/read transitions.
The CY7C1354D are pin compatible and functionally equivalent
to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354D) and a write enable (WE) input. All
writes are conducted with on-chip synchronous self-timed write
circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
For a complete list of related documentation, click here.
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
BW c
BW d
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-88918 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 27, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1354D Datasheet

9-Mbit (256K x 36) Pipelined SRAM

No Preview Available !

CY7C1354D
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Burst Read Accesses .................................................. 5
Single Write Accesses ................................................. 5
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 6
Linear Burst Address Table ......................................... 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Partial Truth Table for Read/Write .................................. 8
IEEE 1149.1 Serial Boundary Scan (JTAG) .................... 9
Disabling the JTAG Feature ........................................ 9
Test Access Port (TAP) ............................................... 9
PERFORMING A TAP RESET .................................... 9
TAP REGISTERS ........................................................ 9
TAP Instruction Set ................................................... 10
TAP Controller State Diagram ....................................... 11
TAP Controller Block Diagram ...................................... 12
TAP Timing ...................................................................... 12
TAP AC Switching Characteristics ............................... 13
3.3 V TAP AC Test Conditions ....................................... 13
3.3 V TAP AC Output Load Equivalent ......................... 13
2.5 V TAP AC Test Conditions ....................................... 13
2.5 V TAP AC Output Load Equivalent ......................... 13
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 14
Identification Register Definitions ................................ 15
Scan Register Sizes ....................................................... 15
Instruction Codes ........................................................... 15
Boundary Scan Exit Order ............................................. 16
Maximum Ratings ........................................................... 17
Operating Range ............................................................. 17
Neutron Soft Error Immunity ......................................... 17
Electrical Characteristics ............................................... 17
Capacitance .................................................................... 18
Thermal Resistance ........................................................ 18
AC Test Loads and Waveforms ..................................... 19
Switching Characteristics .............................................. 20
Switching Waveforms .................................................... 21
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagrams .......................................................... 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC®Solutions ....................................................... 28
Cypress Developer Community ................................. 28
Technical Support ..................................................... 28
Document Number: 001-88918 Rev. *B
Page 2 of 28


Part Number CY7C1354D
Description 9-Mbit (256K x 36) Pipelined SRAM
Maker Cypress Semiconductor
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CY7C1354D Datasheet PDF






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