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CY7C1354BV25 Datasheet

Manufacturer: Cypress (now Infineon)
CY7C1354BV25 datasheet preview

Datasheet Details

Part number CY7C1354BV25
Datasheet CY7C1354BV25_CypressSemiconductor.pdf
File Size 518.38 KB
Manufacturer Cypress (now Infineon)
Description 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354BV25 page 2 CY7C1354BV25 page 3

CY7C1354BV25 Overview

They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and CY7C1356BV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.

CY7C1354BV25 Key Features

  • Pin-patible and functionally equivalent to ZBT™
  • Supports 225-MHz bus operations with zero wait states
  • Available speed grades are 225, 200 and 166 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte Write capability
  • Single 2.5V power supply
  • Fast clock-to-output times
  • 2.8 ns (for 225-MHz device)
  • 3.2ns (for 200-MHz device)
Cypress (now Infineon) logo - Manufacturer

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CY7C1354BV25 Distributor

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