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Cypress Semiconductor Electronic Components Datasheet

CY7C1354BV25 Datasheet

256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture

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CY7C1354BV25
CY7C1356BV25
256K x 36/512K x 18 Pipelined SRAM with
NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT™
• Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200 and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354BV25 and
CY7C1356BV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354BV25
and CY7C1356BV25 are pin compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packag-
es
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1354BV25 and BWa–BWb for
CY7C1356BV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1354BV25 (256K x 36)
CLK
CEN
A0, A1, A
MODE
C
ADV/LD
BWa
BWb
BWc
BWd
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
READ LOGIC
SLEEP
CONTROL
DQs
DQPa
DQPb
DQPc
DQPd
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05292 Rev. *E
Revised August 10, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1354BV25 Datasheet

256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture

No Preview Available !

CY7C1354BV25
CY7C1356BV25
Logic Block Diagram-CY7C1356BV25 (512K x 18)
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Selection Guide
CY7C1354BV25-225 CY7C1354BV25-200 CY7C1354BV25-166
CY7C1356BV25-225 CY7C1356BV25-200 CY7C1356BV25-166
Maximum Access Time
2.8 3.2 3.5
Maximum Operating Current
250 220 180
Maximum CMOS Standby Current
35 35 35
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Unit
ns
mA
mA
Document #: 38-05292 Rev. *E
Page 2 of 27


Part Number CY7C1354BV25
Description 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
Maker Cypress Semiconductor
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Cypress Semiconductor





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