CY7C1354C Description
CY7C1354C CY7C1356C 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™.
CY7C1354C Key Features
- Pin-patible and functionally equivalent to ZBT
- Supports 250 MHz bus operations with zero wait states
- Available speed grades are 250, 200, and 166 MHz
- Internally self-timed output buffer control to eliminate the need
- Fully registered (inputs and outputs) for pipelined operation
- Byte write capability
- Single 3.3 V power supply (VDD)
- 3.3 V or 2.5 V I/O power supply (VDDQ)
- Fast clock-to-output times
- 2.8 ns (for 250 MHz device)