900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Cypress Semiconductor Electronic Components Datasheet

CY7C1354C Datasheet

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

No Preview Available !

CY7C1354C
CY7C1356C
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible and functionally equivalent to ZBT
Supports 250 MHz bus operations with zero wait states
Available speed grades are 250, 200, and 166 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
Single 3.3 V power supply (VDD)
3.3 V or 2.5 V I/O power supply (VDDQ)
Fast clock-to-output times
2.8 ns (for 250 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in Pb-free 100-pin TQFP package, Pb-free, and non
Pb-free 119-ball BGA package and 165-ball FBGA package
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1354C/CY7C1356C[1] are 3.3 V,
256K × 36/512K × 18 synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The CY7C1354C/CY7C1356C
are equipped with the advanced (NoBL) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature greatly improves the throughput
of data in systems that require frequent write/read transitions.
The CY7C1354C/CY7C1356C are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354C and BWa–BWb for CY7C1356C)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.8
250
40
200 MHz
3.2
220
40
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05538 Rev. *S
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1354C Datasheet

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

No Preview Available !

CY7C1354C
CY7C1356C
Logic Block Diagram – CY7C1354C
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
BW c
BW d
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Logic Block Diagram – CY7C1356C
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
O
U
T
S
E
N
P
U
T
MEMORY
ARRAY
S
E
A
M
P
S
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
READ LOGIC
Sleep
Control
Document Number: 38-05538 Rev. *S
Page 2 of 36


Part Number CY7C1354C
Description 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Maker Cypress Semiconductor
PDF Download

CY7C1354C Datasheet PDF






Similar Datasheet

1 CY7C1354B 9-Mb (256K x 36/512K x 18) Pipelined SRAM
Cypress Semiconductor
2 CY7C1354BV25 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
Cypress Semiconductor
3 CY7C1354C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Cypress Semiconductor
4 CY7C1354CV25 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Cypress Semiconductor
5 CY7C1354D 9-Mbit (256K x 36) Pipelined SRAM
Cypress Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy