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Cypress Semiconductor Electronic Components Datasheet

CY7C1338 Datasheet

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

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CY7C1338
128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
Features
Functional Description
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 128K by 32 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wraparound counter supporting either inter-
leaved or linear burst sequence
• Separate processor and controller address strobes pro-
vide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• 3.3V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
The CY7C1338 is a 3.3V, 128K by 32 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1338 allows both interleaved and linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A[16:0]
GW
BWE
BW 3
BW 2
17
BW 1
BW 0
CE1
CE2
CE3
MODE
(A0,A1) 2
BURST Q0
CE COUNTER
CLR
Q1
Q
ADDRESS
CE
D
REGISTER
15
D DQ[31:24] Q
BYTEWRITE
REGISTERS
D DQ[23:16] Q
BYTEWRITE
REGISTERS
D DQ[15:8] Q
BYTEWRITE
REGISTERS
D DQ[7:0] Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
15
17
128K X 32
MEMORY
ARRAY
32 32
OE
ZZ SLEEP
CONTROL
INPUT
REGISTERS
CLK
DQ[31:0]
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Intel and Pentium are registered trademarks of Intel Corporation.
7C1338-117
7.5
350
2.0
7C1338-100
8.0
325
2.0
7C1338-90
8.5
300
2.0
7C1338-50
11.0
250
2.0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 5, 2000


Cypress Semiconductor Electronic Components Datasheet

CY7C1338 Datasheet

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

No Preview Available !

Pin Configuration
BYTE2
BYTE3
NC
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-Lead TQFP
CY7C1338
CY7C1338
80 NC
79 DQ15
78 DQ14
77 VDDQ
76 VSSQ
75 DQ13
74 DQ12
73 DQ11
72 DQ10
71 VSSQ
70 VDDQ
69 DQ9
68 DQ8
67 VSS
66 NC
65 VDD
64 ZZ
63 DQ7
62 DQ6
61 VDDQ
60 VSSQ
59 DQ5
58 DQ4
57 DQ3
56 DQ2
55 VSSQ
54 VDDQ
53 DQ1
52 DQ0
51 NC
BYTE1
BYTE0
2


Part Number CY7C1338
Description 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
Maker Cypress Semiconductor
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CY7C1338 Datasheet PDF






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