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Cypress Semiconductor Electronic Components Datasheet

CY7C133 Datasheet

2K x 16 Dual-Port Static RAM

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CY7C133
CY7C143
2K x 16 Dual-Port Static RAM
Features
True dual-ported memory cells which allow
simultaneous reads of the same memory location
2K x 16 organization
0.65-micron CMOS for optimum speed/power
High-speed access: 25/35/55 ns
Low operating power: ICC = 150 mA (typ.)
• Fully asynchronous operation
Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
BUSY output flag on CY7C133; BUSY input flag on
CY7C143
Available in 68-pin PLCC
Logic Block Diagram
CEL
R/WLUB
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting
independent access to any location in memory. The CY7C133
can be utilized as either a stand-alone 16-bit dual-port static
RAM or as a master dual-port RAM in conjunction with the
CY7C143 slave dual-port device in systems requiring 32-bit or
greater word widths. It is the solution to applications requiring
shared or buffered data, such as cache memory for DSP,
bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/WUB, R/WLB), and Output Enable (OE).
BUSY signals that the port is trying to access the same
location currently being accessed by the other port. An
automatic power-down feature is controlled independently on
each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
CER
R/WRUB
R/WLLB
OEL
R/WRLB
OER
I/O8L – I/O15L
I/O0L – I/O7L
BUSYL[1]
A10L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
CE L
OE L
R/WLUB
R/WLLB
ARBITRATION
LOGIC
(CY7C133 ONLY)
CER
OER
R/WRUB
R/WRLB
Note:
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
I/O8R – I/O15R
I/O0R – I/O7R
1[ ]
BUSYR
A10R
A0R
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06036 Rev. *B
Revised June 22, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C133 Datasheet

2K x 16 Dual-Port Static RAM

No Preview Available !

Pin Configuration
68-Pin LCC/PLCC
Top View
I/O9L
I/O10L
I/O11L
I/O12L
I/O13L
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 7C133 54
17 7C143 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
A6L
A5L
A4L
A3L
A2L
A1L
A0L
BUSYL
CEL
CER
BUSYR
A0R
A1R
A2R
A3R
A4R
A5R
CY7C133
CY7C143
Selection Guide
Maximum Access Time
Typical Operating Current ICC
Typical Standby Current for ISB1
7C133-25
7C143-25
25
170
40
7C133-35
7C143-35
35
160
30
7C133-55
7C143-55
55
150
20
Unit
ns
mA
mA
Document #: 38-06036 Rev. *B
Page 2 of 13


Part Number CY7C133
Description 2K x 16 Dual-Port Static RAM
Maker Cypress Semiconductor
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CY7C133 Datasheet PDF






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