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Cypress Semiconductor Electronic Components Datasheet

CY7C1329 Datasheet

64K x 32 Synchronous-Pipelined Cache RAM

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CY7C1329
64K x 32 Synchronous-Pipelined Cache RAM
Features
• Supports 133-MHz bus for Pentium® and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 4.2 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
— 7.0 ns (for 75-MHz device
• User-selectable burst counter supporting Intel®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A[15:0]
GW
BWE
BW 3
BW2
16
MODE
(A[1:0]) 2
BURST Q0
CE COUNTER
CLR
Q1
Q
ADDRESS
CE
D
REGISTER
14
D DQ[31:24] Q
BYTEWRITE
REGISTERS
D DQ[23:16] Q
BYTEWRITE
REGISTERS
BW1
BW0
CE1
CE2
CE3
D DQ[15:8] Q
BYTEWRITE
REGISTERS
D DQ[7:0] Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 4.2 ns (133-MHz
device).
The CY7C1329 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
14 16
64KX32
MEMORY
ARRAY
32 32
DQ
ENABLE DELAY
REGISTER
CLK
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
OE
ZZ SLEEP
CONTROL
DQ[31:0]
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 6, 1999


Cypress Semiconductor Electronic Components Datasheet

CY7C1329 Datasheet

64K x 32 Synchronous-Pipelined Cache RAM

No Preview Available !

Pin Configuration
100-Pin TQFP
CY7C1329
BYTE2
BYTE3
NC
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1329
80 NC
79 DQ15
78 DQ14
77 VDDQ
76 VSSQ
75 DQ13
74
73
DQ12
DQ11
BYTE1
72 DQ10
71 VSSQ
70 VDDQ
69 DQ9
68 DQ8
67 VSS
66 NC
65 VDD
64 ZZ
63 DQ7
62 DQ6
61 VDDQ
60 VSSQ
59 DQ5
58
DQ4
BYTE0
57 DQ3
56 DQ2
55 VSSQ
54 VDDQ
53 DQ1
52 DQ0
51 NC
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
Commercial
7C1329-133
4.2
325
5
7C1329-100
5.5
310
5
7C1329-75
7.0
260
5
2


Part Number CY7C1329
Description 64K x 32 Synchronous-Pipelined Cache RAM
Maker Cypress Semiconductor
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CY7C1329 Datasheet PDF






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