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CY7C1329 - 64K x 32 Synchronous-Pipelined Cache RAM

Description

The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

Features

  • Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states.
  • Fully registered inputs and outputs for pipelined operation.
  • 64K x 32 common I/O architecture.
  • Single 3.3V power supply.
  • Fast clock-to-output times.
  • 4.2 ns (for 133-MHz device).
  • 5.5 ns (for 100-MHz device).
  • 7.0 ns (for 75-MHz device.
  • User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Features • Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 4.2 ns (for 133-MHz device) — 5.5 ns (for 100-MHz device) — 7.0 ns (for 75-MHz device • User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • JEDEC-standard 100 TQFP pinout • “ZZ” Sleep Mode option and Stop Clock option All synchronous inputs pass through input registers controlled by the rising edge of the clock.
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