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Cypress Semiconductor Electronic Components Datasheet

CY7C1325 Datasheet

256K x 18 Synchronous 3.3V Cache RAM

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CY7C1325
256K x 18 Synchronous
3.3V Cache RAM
Features
Functional Description
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 256K by 18 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
• Separate processor and controller address strobes pro-
vides direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• I/Os capable of 2.5–3.3V operation
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
The CY7C1325 is a 3.3V, 256K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1325 allows both an interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the Cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A[17:0]
GW
BWE
BW 1
18
BW 0
CE1
CE2
CE3
MODE
(A0,A1) 2
BURST Q0
CE COUNTER
CLR
Q1
DaADtaDRSEhSSeeQt4U1.6com
CE
D
REGISTER
16
D DQ[15:8] Q
BYTEWRITE
REGISTERS
D DQ[7:0] Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
18
256K X 18
MEMORY
ARRAY
18 18
DataShee
OE
ZZ SLEEP
CONTROL
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Intel and Pentium are registered trademarks of Intel Corporation.
DataSheet4U.com
7C1325-117
7.5
350
10.0
7C1325-100
8.0
325
10.0
7C1325-80
8.5
300
10.0
INPUT
REGISTERS
CLK
DQ[15:0]
DP[1:0]
7C1325-50
11.0
250
10.0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 10, 2000
DataSheet4 U .com


Cypress Semiconductor Electronic Components Datasheet

CY7C1325 Datasheet

256K x 18 Synchronous 3.3V Cache RAM

No Preview Available !

www.DataSheet4U.com
Pin Configurations
100-Lead TQFP
CY7C1325
et4U.com
BYTE1
NC
NC
NC
VDDQ
VSS
NC
NC
DQ8
DQ9
VSS
VDDQ
DQ10
DQ11
NC
VDD
NC
VSS
DQ12
DQ13
VDDQ
VSS
DQ14
DQ15
DP1
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DataSheet4U.com
CY7C1325
80 A10
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DP0
73 DQ7
72 DQ6
71 VSS
70 VDDQ
69 DQ5
68 DQ4
67 VSS
66 NC
65 VDD
64 ZZ
63 DQ3
62 DQ2
61 VDDQ
60 VSS
59 DQ1
58 DQ0
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
BYTE0
DataShee
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2


Part Number CY7C1325
Description 256K x 18 Synchronous 3.3V Cache RAM
Maker Cypress Semiconductor
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CY7C1325 Datasheet PDF






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