CY7C1141V18
Overview
- 300 MHz to 375 MHz clock for high bandwidth
- 4-Word Burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz
- Read latency of 2.0 clock cycles
- Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for both read and write ports
- Separate Port Selects for depth expansion
- Data valid pin (QVLD) to indicate valid data on the output
- Synchronous internally self-timed writes
