* Organization: 131,072 words × 32 or 36 bits NTD™1 architecture for efficient bus operation
* Fast clock speeds to 166 MHz in LVTTL/LVCMOS
* Fast clock to da.

requiring random access or read-modify-write operations. NTD devices use the memory bus more efficiently by introducing .

The AS7C33128NTD36A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words × 32 or 36 bits that incorporates a LATE LATE Write. This variation of the 4Mb sychronous SRAM uses the No T.

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