AS7C33128NTF18B sram equivalent, 3.3v 128k x 18 flowthrough synchronous sram.
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* Organization: 131,072 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10..
requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing.
The AS7C33128NTF18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE Write. This variation of the 2Mb+ synchronous SRAM uses the No Turnaround Delay (.
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