Description
February 2005 ® AS7C33128NTD32B AS7C33128NTD36B 3.3V 128K×32/36 Pipelined SRAM with NTDTM .
The AS7C33128NTD36B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 32 or 36 bits.
Features
* Organization: 131,072 words × 32 or 36 bits
* NTD™ architecture for efficient bus operation
* Fast clock speeds to 200 MHz
* Fast clock to data access: 3.0/3.5/4.0 ns
* Fast OE access time: 3.0/3.5/4.0 ns
* Fully synchronous operation
* Async
Applications
* requiring random access or read-modify-write operations. www. DataSheet4U. com pipeline
NTD™ devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one) cycle (flowthrough) read latency. Write data is applied two cycles after the write command and address,
