Description
December 2002 AS7C33256NTD16A AS7C33256NTD18A ® 9 .î 65$0 ZLWK 17'TM .
The AS7C33256NTD16A/18A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 16 or 18.
Features
* Organization: 262,144 words × 16 or 18 bits
* NTD™1 architecture for efficient bus operation
* Fast clock speeds to 166 MHz in LVTTL/LVCMOS
* Fast clock to data access: 3.5/4.0/5.0 ns
* Fast OE access time: 3.5/4.0/5.0 ns
* Fully synchronous operatio
Applications
* requiring random access or Read-ModifyWrite operations. NTD devices use the memory bus more efficiently by introducing a write latency that matches the two-cycle pipelined or one-cycle flowthrough read latency. Write data is applied two cycles after the Write command and address, allowing the Read p
