AS7C33128NTD18B sram equivalent, 3.3v 128kx18 pipelined sram.
* Organization: 131,072 words × 18 bits
* NTD™ architecture for efficient bus operation
* Fast clock speeds to 200 MHz
* Fast clock to data access: 3.0/3..
requiring random access or Read-Modify-Write operations. NTD™ devices use the memory bus more efficiently by introducing.
The AS7C33128NTD18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE LATE Write. This variation of the 2Mb sychronous SRAM uses the No Turnaround Dela.
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