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AS7C33128NTD18B 3.3V 128Kx18 Pipelined SRAM

AS7C33128NTD18B Description

April 2005 ® AS7C33128NTD18B 3.3V 128K×18 Pipelined SRAM with NTDTM .
The AS7C33128NTD18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and i.

AS7C33128NTD18B Features

* Organization: 131,072 words × 18 bits
* NTD™ architecture for efficient bus operation
* Fast clock speeds to 200 MHz
* Fast clock to data access: 3.0/3.5/4.0 ns
* Fast OE access time: 3.0/3.5/4.0 ns
* Fully synchronous operation
* Asynchronou

AS7C33128NTD18B Applications

* requiring random access or Read-Modify-Write operations. NTD™ devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle pipeline (flowthrough) read latency. Write data is applied two cycles after the Write command and address, allowing the Read www

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3.3V 128Kx18 Pipelined SRAM Alliance Semiconductor Corporation
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