AS4C1G8D3LA sdram equivalent, 8gbit ddr3l sdram.
- Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe-
lined architecture
- Bi-direct.
Pin
CK, CK CKE
CS ODT RAS, CAS, WE DM BA0 - BA2 A0 - A15
A10 / AP
A12 / BC RESET
DQ DQS, DQS
NC
Type
Input
Input
Input Input
Input Input Input
Input
Input
Input Input
Input/ Output Input/ Output
Function
Clock : CK and CK are differential clock in.
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