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Cypress Semiconductor Electronic Components Datasheet

W199 Datasheet

Spread Spectrum FTG for VIA Apollo Pro-133

No Preview Available !

W199 pdf
PRELIMINARY
W199
Spread Spectrum FTG for VIA Apollo Pro-133
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Single-chip system frequency synthesizer for VIA
Apollo Pro-133
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• 13 SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 150 MHz
• I2C™ interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAMIN to SDRAM0:11 Delay: ..........................3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin 2
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
CPU_F,
FS3 FS2 FS1 FS0 CPU1 (MHz)
111 1
133.3
111 0
124
110 1
150
110 0
140
101 1
105
101 0
110
100 1
115
100 0
120
011 1
100
011 0
133.3
010 1
112
010 0
103
001 1
66.8
001 0
83.3
000 1
75
000 0
124
PCI_F, 1:5
(MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Logic Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
CLK_STOP#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
I2C
Logic
PLL2
Stop
Clock
Control
÷2
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU1
CPU_F
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS0
Pin Configuration[1]
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1/FS3
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
{I2C SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU_F
43 CPU1
42 VDDQ2
41 CLK_STOP#
40 SDRAM_F
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
SDRAMIN
Stop
Clock
Control
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
I2C is a trademark of Philips Corporation.
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 19, 1999, rev. **



Cypress Semiconductor Electronic Components Datasheet

W199 Datasheet

Spread Spectrum FTG for VIA Apollo Pro-133

No Preview Available !

W199 pdf
PRELIMINARY
W199
Pin Definitions
Pin Name
CPU_F
Pin No.
44
CPU1
43
PCI2:5
PCI1/FS3
10, 11, 12,
13
8
PCI_F/MODE
7
CLK_STOP#
41
IOAPIC
48MHz/FS0
47
26
24MHz/FS1
25
REF1/FS2
46
REF0/
(PCI_STOP#)
2
SDRAMIN
15
SDRAM0:11
SDRAM_F
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17
40
SCLK
SDATA
X1
24
23
4
X2
VDDQ3
VDDQ2
GND
5
1, 6, 14, 19,
27, 30, 36
42, 48
3, 9, 16, 22,
33, 39, 45
Pin
Type
Pin Description
O Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to
VDDQ2. See Tables 2 and 6 for detailed frequency information.
O CPU Clock Output 1: This CPU clock output is controlled by the CLK_STOP# control
pin. Output voltage swing is controlled by voltage applied to VDDQ2.
O PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3.
I/O Fixed PCI Clock Output: As an output. frequency is set by the FS0:3 inputs or through
serial input interface, see Tables 2 and 6. This output is affected by the PCI_STOP#
input. When an input, latches data selecting the frequency of the CPU and PCI outputs.
I/O Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through
serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP#
input. When an input, sets function of pin 2.
I CLK_STOP# Input: When brought LOW, affected clock outputs are stopped LOW after
completing a full clock cycle (23 CPU clock latency). When brought HIGH, affected
clock outputs start, beginning with a full clock cycle (23 CPU clock latency).
O IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing
is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW.
I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this
output can be used as the reference for the Universal Serial Bus. Upon power-up FS0
input will be latched, which will set clock frequencies as described in Table 2.
I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this
output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will
be latched, which will set clock frequencies as described in Table 2.
I/O I/O Dual-Function REF0 and FS2 pin: Upon power-up, FS2 input will be latched which
will set clock frequencies as described in Table 2. When an output, this pin provides a
fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins.
I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin.
The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to
remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of
PCI_F. Its effects take place on the next PCI_F clock cycle. When an output, this pin
provides a fixed clock signal equal in frequency to the reference signal provided at the
X1/X2 pins.
I Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:11, SDRAM_F).
O Buffered Outputs: These twelve dedicated outputs provide copies of the signal provid-
ed at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when
CLK_STOP# input is set LOW.
O Free-running Buffered Output: This dedicated output provides a copy of the SDRAMIN
input which is not affected by the CLK_STOP# input
I Clock pin for I2C circuitry.
I/O Data pin for I2C circuitry.
I Crystal Connection or External Reference Frequency Input: This pin has dual func-
tions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
P Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI
outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply
P Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers. Con-
nect to 2.5V or 3.3V.
G Ground Connections: Connect all ground pins to the common system ground plane.
2



Cypress Semiconductor Electronic Components Datasheet

W199 Datasheet

Spread Spectrum FTG for VIA Apollo Pro-133

No Preview Available !

W199 pdf
PRELIMINARY
W199
Overview
The W199 was developed as a single-chip device to meet the
clocking needs of the VIA Apollo Pro-133 core logic chip set.
In addition to the typical outputs provided by standard
100-MHz FTGs, the W199 adds a thirteenth output buffer, sup-
porting SDRAM DIMM modules in conjunction with the
chipset.
Cypresss proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When en-
abled, this feature reduces the peak EMI measurements of not
only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 7, 8, 25, 26, are 46 are dual-purpose l/O pins. Upon pow-
er-up these pins act as logic inputs, allowing the determination
of assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-kstrappingresistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to 0,connection to VDD sets a latch to 1.Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W199 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the five I/O pins (7, 8,
25, 26, 46) are three-stated, allowing the output strapping re-
sistor on the l/O pins to pull the pins and their associated ca-
pacitive clock load to either a logic HIGH or LOW state. At the
end of the 2-ms period, the established logic 0or 1condi-
tion of the l/O pin is latched. Next the output buffer is enabled,
converting the l/O pins into operating clock outputs. The 2-ms
timer starts when VDD reaches 2.0V. The input bits can only
be reset by turning VDD off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock outputs is <40(nominal), which is minimally
affected by the 10-kstrap to ground or VDD. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length to
minimize system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the corresponding specified output frequency is deliv-
ered on the pin, assuming that VDD has stabilized. If VDD has
not yet reached full value, output frequency initially may be
below target but will increase to target once VDD voltage has
stabilized. In either case, a short output clock cycle may be
produced from the CPU clock outputs when the outputs are
enabled.
W199
Power-on
Reset
Timer
VDD
Output
Buffer
Output Three-state Hold
Output
Low
QD
Data
Latch
10 k
(Load Option 1)
10 k
(Load Option 0)
Output Strapping R esistor
Series Term ination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
W199
Power-on
Reset
Timer
Output
Buffer
Output Three-state Hold
Output
Low
QD
D a ta
Latch
10 k
VDD Output Strapping Resistor
Series Termination Resistor
R Clock Load
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
3




Part Number W199
Description Spread Spectrum FTG for VIA Apollo Pro-133
Maker Cypress Semiconductor
Total Page 14 Pages
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