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Cypress Semiconductor Electronic Components Datasheet

W196 Datasheet

Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

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W196 pdf
PRELIMINARY
W196
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for 440BX, 440ZX, and
VIA Apollo Pro-133
• I2C programmable to 155 MHz (32 selectable
frequencies)
• Two skew-controlled copies of CPU output
• Seven copies of PCI output (synchronous w/CPU out-
put)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock is determined by resistor
straps on power up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
VDDQ3
REF2X/SEL48#
GND
VDDQ3
IOAPIC
FS1 PLL 1
FS0
÷2/÷3
SDATA
SCLOCK
I2C
LOGIC
VDDQ2
CPU0
CPU1
GND
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
GND
CPU Cycle to Cycle Jitter: .......................................... 250 ps
CPU, PCI Output Edge Rate: ......................................... ≥1 V/ns
CPU0:1 Output Skew: ................................................ 175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA: ............... 250-kpull-up
FS1: ............................................................250-kpull-down
FS0: ...................................................No pull-up or pull-down
Note: Internal pull-up or pull-down resistors should not be re-
lied upon for setting I/O pins HIGH or LOW.
Table 1. Pin Selectable Frequency
FS1 FS0 CPU(0:1) PCI
1 1 133.3 MHz 33.3 MHz
1
0
105 MHz
35 MHz
0
1
100 MHz
33.3 MHz
0 0 66.8 MHz 33.3 MHz
Pin Configuration
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24_48MHz/FS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 REF2X/SEL48#
26 VDDQ3
25 VDDQ2
24 IOAPIC
23 VDDQ2
22 CPU0
21 CPU1
20 VDDQ3
19 GND
18 SDATA
17 SCLOCK
16 FS0
15 GND
PLL2
VDDQ3
48MHz
24_48MHz/FS1
GND
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 28, 1999, rev. **


Cypress Semiconductor Electronic Components Datasheet

W196 Datasheet

Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

No Preview Available !

W196 pdf
PRELIMINARY
W196
Pin Definitions
Pin Name
CPU0:1
Pin
No.
22, 21
PCI1:6
PCI_F
5, 6, 7, 8, 10,
11, 4
IOAPIC
24
48MHz
13
24_48MHz/FS1
14
REF2X/SEL48#
27
FS0
SDATA
SCLOCK
X1
X2
VDDQ3
VDDQ2
GND
16
18
17
1
2
9, 12, 20, 26
23, 25
3, 15, 19, 28
Pin
Type
O
O
O
O
I/O
I/O
I
I/O
I
I
I
P
P
G
Pin Description
CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by
FS0:1 or the serial data interface. See Table 1 and Table 5. Output voltage swing is
set by the voltage applied to VDDQ2.
PCI Bus Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs
run synchronously to the CPU clock. Voltage swing is set by the power connection
to VDDQ3.
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24-MHz or 48-MHz Output/Frequency Select 1 Input: Frequency is set by the state
of pin 27 on power-up. This pin doubles as the select strap to determine device
operating frequency as described in Table 1.
I/O Dual-Function REF2X and SEL48# Pin: Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD, pin
14 will output 2 4MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
Frequency Selection 0 Input: Selects CPU clock frequency as shown in Table 1
on page 1.
I2C Data Pin: Data should be presented to this input as described in the I2C section
of this data sheet. Internal 250-kpull-up resistor.
I2C Clock Pin: The I2C Data clock should be presented to this input as described in
the I2C section of this data sheet.
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection: Power supply for core logic and PLL circuitry, PCI, 48/24MHz,
and Reference output buffers. Connect to 3.3V supply.
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to
2.5V supply.
Ground Connections: Connect all ground pins to the common system ground
plane.
2


Part Number W196
Description Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Maker Cypress Semiconductor
Total Page 11 Pages
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