Pipelined Datasheet | Specifications & PDF Download

1CY7C1380BV25 PRELIMINARY CY7C1380BV25 CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200,166,

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IS61VPD25636A IS61LPD25636A IS61VPD51218A IS61LPD51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.DataShe

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM64PC32T/D Advance Information 256K/512K Pipelined BurstRAM™ Secondary Cache Module

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IS61SPS25632T/D IS61LPS25632T/D IS61SPS25636T/D IS61LPS25636T/D IS61SPS51218T/D IS61LPS51218T/D 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE,

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IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 128K x 32, 128K x 36, 256K x 18 DECEMBER 2013 4 Mb SYNCHR

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CY7C1460SV25 CY7C1462SV25 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Archit

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CY7C1380C CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz • Available

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CY7C1303BV18 CY7C1306BV18 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture Features Functional Description • Separate independent Read and

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www.DataSheet4U.com PREMILINARY CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features • Separate independent Read and Wr

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CY7C1370B CY7C1372B 512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycle

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GS8320Z18/36T-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAMs 250 MHz–13

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IS61VPD25636A IS61LPD25636A IS61VPD51218A IS61LPD51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.DataShe

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GS8320Z18/36T-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAMs 250 MHz–13

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GS8160FZ18/36DGT-6.5 100-Pin TQFP Commercial Temp Industrial Temp 18Mb Pipelined and Flow Through Synchronous NBT SRAMs 6.5 ns 2.5 V or 3.3 V VDD 2

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IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.Data

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IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 128K x 32, 128K x 36, 256K x 18 DECEMBER 2013 4 Mb SYNCHR

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GS8320Z18/36T-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAMs 250 MHz–13

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CY7C1370KV25 CY7C1372KV25 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Ar

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www.DataSheet4U.com A67L1618/A67L0636 Series Preliminary Document Title 2M X 16, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 0

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