Cypress Semiconductor CY7 Datasheet | Specifications & PDF Download

CY7C4425/4205/4215 CY7C4225/4235/4245 64/256/512/1K/2K/4K x 18 Synchronous FIFOs Features ■ High speed, low power, first-in first-out (FIFO) memories

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USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C344B 32-Macrocell MAX® EPLD Features • High-performance, high-density replacement for TTL, 74HC, and custom

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CY7C43642AV CY7C43662AV CY7C43682AV 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO Features • 3.3V high-speed, low-power, bidirectional, First-

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CY7C25632KV18 CY7C25652KV18 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Four-Word Burs

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CY7C1563XV18/CY7C1565XV18 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit QDR® II+ Xtreme SRAM Four-Word B

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CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 72-Mbit QDR® II SRAM Four-Word Burst Architecture 72-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■

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CY7C25422KV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (

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1CY 7C42 65 fax id: 5413 PRELIMINARY CY7C4255 CY7C4265 8K/16Kx18 Deep Sync FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memor

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CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two

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1CY7C266 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed —

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1CY7C274 CY7C271 CY7C274 32K x 8 Power Switched and Reprogrammable PROM Features • CMOS for optimum speed/power • Windowed for reprogrammability • H

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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features ■ ■ Functional Description

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CY7C1522KV18, CY7C1529KV18 CY7C1523KV18, CY7C1524KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture 72-Mbit DDR II SIO SRAM 2-Word Burst Architec

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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CY7C1305BV18 CY7C1307BV18 18-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture Features Functional Description • Separate independent Read and

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PRELIMINARY CY7C1481V33 CY7C1483V33 CY7C1487V33 2M x 36/4M x 18/1M x 72 Flow-through SRAM Features • Supports 133-MHz bus operations • 2M x 36/4M x

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CY7C1510AV18, CwYww7.DCat1a5Sh2ee5t4AU.Vco1m8 CY7C1512AV18, CY7C1514AV18 72-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Separate independe

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www.DataSheet4U.com CY7C0430BV CY7C0430CV 10 Gb/s 3.3V QuadPort™ DSE Family Features • QuadPort™ datapath switching element (DSE) family allows four

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