CY7C2262XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Part number	CY7C2262XV18
Manufacturer	Cypress Semiconductor
File Size	647.92 KB
Description	36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
Datasheet	CY7C2262XV18-CypressSemiconductor.pdf

Separate independent read and write data ports.
Supports concurrent transactions.
450 MHz clock for high bandwidth.
2-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed system.

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Published: Mar 14, 2017 |