CY7C2263XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Part number	CY7C2263XV18
Manufacturer	Cypress Semiconductor
File Size	1.07 MB
Description	36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
Datasheet	CY7C2263XV18-CypressSemiconductor.pdf

Separate independent read and write data ports.
Supports concurrent transactions.
633 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed sy.

📁 CY7C2263XV18 Similar Datasheet

Other Datasheets by Cypress Semiconductor

Published: Mar 14, 2017 |