Cypress CY7 Datasheet | Specifications & PDF Download

CY7C25422KV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (

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CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two

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CY7C25632KV18 CY7C25652KV18 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Four-Word Burs

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CY7C4425/4205/4215 CY7C4225/4235/4245 64/256/512/1K/2K/4K x 18 Synchronous FIFOs Features ■ High speed, low power, first-in first-out (FIFO) memories

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CY7C43642AV CY7C43662AV CY7C43682AV 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO Features • 3.3V high-speed, low-power, bidirectional, First-

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CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ 144-Mbit densi

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CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 72-Mbit QDR® II SRAM Four-Word Burst Architecture 72-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■

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CY7C1522JV18, CY7C1529JV18 CY7C1523JV18, CY7C1524JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description Th

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CY7C1510AV18, CwYww7.DCat1a5Sh2ee5t4AU.Vco1m8 CY7C1512AV18, CY7C1514AV18 72-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Separate independe

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture 72-Mbit DDR II SRAM Four-Word Burst Architecture Features ■ 72-Mbit Density (2M × 36) ■

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82A CY7C281A CY7C282A 1K x 8 PROM Features • CMOS for optimum speed/power • High speed — 25 ns (commercial) — 30 ns (military) • Low power — 495 mW

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CY7C1460BV25 CY7C1462BV25 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Ar

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USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C344B 32-Macrocell MAX® EPLD Features • High-performance, high-density replacement for TTL, 74HC, and custom

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1CY 7C42 65 fax id: 5413 PRELIMINARY CY7C4255 CY7C4265 8K/16Kx18 Deep Sync FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memor

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CY7C43642 CY7C43662 CY7C43682 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO Features • High-speed, low-power, bidirectional, First-In, First-Out (F

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CY7C4221 CY7C42311 K / 2 K × 9 Synchronous FIFOs CY7C4221 / CY7C4231 1 K / 2 K × 9 Synchronous FIFOs 1 K / 2 K × 9 Synchronous FIFOs Features ■ High

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CY7C1613KV18/CY7C1615KV18 144-Mbit QDR® II SRAM Four-Word Burst Architecture 144-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate i

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CY7C1518KV18 CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture Features ■ 72-Mbit density

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1CY7C266 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed —

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