Datasheet4U Logo Datasheet4U.com

74ALVCH16823DGG - 18-bit bus-interface D-type flip-flop

Download the 74ALVCH16823DGG datasheet PDF. This datasheet also covers the 74ALVCH16823 variant, as both devices belong to the same 18-bit bus-interface d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.

Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs.

Features

  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low-power consumption.
  • Direct interface with TTL levels.
  • Current drive ± 24 mA at 3.0 V.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ALVCH16823-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74ALVCH16823 18-bit bus-interface D-type flip-flop NXP
74ALVCH16821 20-bit bus-interface D-type flip-flop NXP
74ALVCH16825 18-bit buffer/driver NXP
74ALVCH16827 20-bit buffer/line driver NXP
74ALVCH16841 20-bit bus interface D-type latch NXP

Other Datasheets by nexperia

Part Number Description
74ALVCH16823 18-bit bus-interface D-type flip-flop
74ALVCH16821 20-bit bus-interface D-type flip-flop
74ALVCH16821DGG 20-bit bus-interface D-type flip-flop
74ALVCH16825 18-bit buffer/driver
74ALVCH16825DGG 18-bit buffer/driver

Full PDF Text Transcription

Click to expand full text
74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Rev. 3 — 1 February 2018 Product data sheet 1 General description The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clockenable (nCE) input are provided for each total 9-bit section.
Published: |