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74ALVCH16821
20-bit bus-interface D-type flip-flop; positive-edge trigger;
3-state
Rev. 3 — 2 February 2018
Product data sheet
1 General description
The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each nDn input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s nQn output.
When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.
74ALVCH16821 Datasheet
