Datasheet4U Logo Datasheet4U.com

74AHCT374 - Octal D-type flip-flop

Download the 74AHCT374 datasheet PDF. This datasheet also covers the 74AHC374 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Features

  • I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Common 3-state output enable input I Input levels: N For 74AHC374: CMOS level N For 74AHCT374: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from.
  • 40 °C to +85 °C and from.
  • 40 °C to +125 °C Nexperia 74AHC374; 74AHCT374 Octal D-type fli.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC374-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74AHCT374 Octal D-type flip-flop NXP
74AHCT373 Octal D-type transparent latch NXP
74AHCT30 8-input NAND gate NXP
74AHCT32 Quad 2-input OR gate NXP
74AHCT32 QUADRUPLE 2-INPUT OR GATE Diodes

Other Datasheets by nexperia

Part Number Description
74AHCT374-Q100 Octal D-type flip-flop
74AHCT374D Octal D-type flip-flop
74AHCT374PW Octal D-type flip-flop
74AHCT377 Octal D-type flip-flop
74AHCT377-Q100 Octal D-type flip-flop

Full PDF Text Transcription

Click to expand full text
74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 03 — 12 June 2008 Product data sheet 1. General description The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition. When OE is LOW the content of the eight flip-flops is available at the outputs.
Published: |