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74AHCT374-Q100 - Octal D-type flip-flop

Download the 74AHCT374-Q100 datasheet PDF. This datasheet also covers the 74AHC374-Q100 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

The 74AHC374-Q100; 74AHCT374-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from 40 C to +85 C and from 40 C to +125 C.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger actions.
  • Inputs accept voltages higher than VCC.
  • Common 3-state output enable input.
  • Input levels:.
  • For 74AHC374-Q100: CMOS level.
  • For 74AHCT374-Q100: TTL level.
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.
  • HBM JESD22-A114F exceeds 2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC374-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by nexperia

Part Number Description
74AHCT374 Octal D-type flip-flop
74AHCT374D Octal D-type flip-flop
74AHCT374PW Octal D-type flip-flop
74AHCT377 Octal D-type flip-flop
74AHCT377-Q100 Octal D-type flip-flop

Full PDF Text Transcription

Click to expand full text
74AHC374-Q100; 74AHCT374-Q100 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 1 — 11 March 2014 Product data sheet 1. General description The 74AHC374-Q100; 74AHCT374-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC374-Q100; 74AHCT374-Q100 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition.
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