74AHC02D - Quad 2-input NOR gate

Nexperia

Download the 74AHC02D datasheet PDF. This datasheet also covers the 74AHC02 variant, as both devices belong to the same quad 2-input nor gate family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Key Features

Balanced propagation delays.
All inputs have a Schmitt-trigger action.
Inputs accept voltages higher than VCC.
Input levels:.
For 74AHC02: CMOS level.
For 74AHCT02: TTL level.
ESD protection:.
HBM EIA/JESD22-A114E exceeds 2000 V.
MM EIA/JESD22-A115-A exceeds 200 V.
CDM EIA/JESD22-C101C exceeds 1000 V.
Multiple package options.
Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.

📥 Download Datasheet

74AHC02D quad 2-input nor gate by Nexperia - Datasheet Preview — Note: The manufacturer provides a single datasheet file (74AHC02-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	74AHC02D
Manufacturer	Nexperia
File Size	220.68 KB
Description	Quad 2-input NOR gate
Datasheet	74AHC02D Datasheet

Full PDF Text Transcription for 74AHC02D (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 74AHC02D. For precise diagrams, and layout, please refer to the original PDF.

74AHC02; 74AHCT02 Quad 2-input NOR gate Rev. 5 — 11 May 2020 Product data sheet 1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pi...

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on The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. 2. Features and benefits • Balanced propagation delays • All inputs have a Schmitt-trigger action • Inputs accept voltages higher than VCC • Input levels: • For 74AHC02: CMOS level • For 74AHCT02: TTL level • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V • CDM EIA/JESD22-C101C exceeds 1000 V • Multiple package options • Specified from -40 °C to

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	74AHC02	Quad 2-input NOR gate	NXP

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