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74AHC02 - Quad 2-input NOR gate

General Description

The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard No.

7A.

Key Features

  • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger actions.
  • Inputs accepts voltages higher than VCC.
  • For AHC only: operates with CMOS input levels.
  • For AHCT only: operates with TTL input levels.
  • Specified from.
  • 40 to +85 and +125 °C.

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Full PDF Text Transcription for 74AHC02 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 74AHC02. For precise diagrams, and layout, please refer to the original PDF.

INTEGRATED CIRCUITS DATA SHEET 74AHC02; 74AHCT02 Quad 2-input NOR gate Product specification Supersedes data of 1998 Dec 18 File under Integrated Circuits, IC06 1999 Sep 2...

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es data of 1998 Dec 18 File under Integrated Circuits, IC06 1999 Sep 23 Philips Semiconductors Product specification Quad 2-input NOR gate FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accepts voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Scho

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