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SN74AUP1G79 - Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

Description

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications.

This family assures a very-low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, thus resulting in an increased battery life.

Features

  • 1 Available in the Texas Instruments NanoStar™ Package.
  • Low Static-Power Consumption: ICC = 0.9 µA Maximum.
  • Low Dynamic-Power Consumption: Cpd = 3 pF Typical at 3.3 V.
  • Low Input Capacitance: Ci = 1.5 pF Typical.
  • Low Noise: Overshoot and Undershoot < 10% of VCC.
  • Ioff Supports Partial Power-Down-Mode Operation.
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V.

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Full PDF Text Transcription

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Product Folder Order Now Technical Documents Tools & Software Support & Community SN74AUP1G79 SCES592I – JULY 2004 – REVISED SEPTEMBER 2017 SN74AUP1G79 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop 1 Features •1 Available in the Texas Instruments NanoStar™ Package • Low Static-Power Consumption: ICC = 0.9 µA Maximum • Low Dynamic-Power Consumption: Cpd = 3 pF Typical at 3.3 V • Low Input Capacitance: Ci = 1.5 pF Typical • Low Noise: Overshoot and Undershoot < 10% of VCC • Ioff Supports Partial Power-Down-Mode Operation • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V) • Wide Operating VCC Range of 0.8 V to 3.6 V • Optimized for 3.3-V Operation • 3.
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