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SCAN921226 - 30-80 MHz 10-Bit Bus LVDS Serializer and Deserializer

Download the SCAN921226 datasheet PDF. This datasheet also covers the SCAN921025 variant, as both devices belong to the same 30-80 mhz 10-bit bus lvds serializer and deserializer family and are provided as variant models within a single manufacturer datasheet.

Description

The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock.

The SCAN921226 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock.

Features

  • 1.
  • 2 IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode.
  • Clock Recovery From PLL Lock to Random Data Patterns.
  • Specified Transition Every Data Transfer Cycle.
  • Chipset (Tx + Rx) Power Consumption < 600 mW (typ) @ 80 MHz.
  • Single Differential Pair Eliminates Multi- Channel Skew.
  • 800 Mbps Serial Bus LVDS Data Rate (At 80 MHz Clock).
  • 10-Bit Parallel Interface for 1 Byte Data Plus 2 Control Bits.
  • Synchronization Mode and LO.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SCAN921025-etcTI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NRND SCAN921025, SCAN921226 www.ti.com SNLS148C – DECEMBER 2001 – REVISED APRIL 2013 SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST Check for Samples: SCAN921025, SCAN921226 FEATURES 1 •2 IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode. • Clock Recovery From PLL Lock to Random Data Patterns.
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