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CDCLVD2108 - Dual 1:8 Low Additive Jitter LVDS Buffer

Datasheet Summary

Description

The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15).

Each buffer block consists of one input and 8 LVDS outputs.

The inputs can either be LVDS, LVPECL, or LVCMOS.

Features

  • 1.
  • Dual 1:8 Differential Buffer.
  • Low Additive Jitter.

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Datasheet Details

Part number CDCLVD2108
Manufacturer Texas Instruments
File Size 1.88 MB
Description Dual 1:8 Low Additive Jitter LVDS Buffer
Datasheet download datasheet CDCLVD2108 Datasheet
Additional preview pages of the CDCLVD2108 datasheet.

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Full PDF Text Transcription

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CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • Dual 1:8 Differential Buffer • Low Additive Jitter <300 fs RMS in 10 kHz to 20 MHz • Low Within Bank Output Skew of 50 ps (Max) • Universal Inputs Accept LVDS, LVPECL, LVCMOS • One Input Dedicated for Eight Outputs • Total of 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible • Clock Frequency up to 800 MHz • 2.375–2.
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