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SY10ELT23 - DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR

This page provides the datasheet information for the SY10ELT23, a member of the SY100ELT23 DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR family.

Description

The SY10/100ELT23 are dual differential PECL-to-TTL translators.

Because PECL (Positive ECL) levels are used, only +5V and ground are required.

Features

  • s s s s s s s 3.0ns typical propagation delay.

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Datasheet preview – SY10ELT23

Datasheet Details

Part number SY10ELT23
Manufacturer Synergy
File Size 116.76 KB
Description DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR
Datasheet download datasheet SY10ELT23 Datasheet
Additional preview pages of the SY10ELT23 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com SEMICONDUCTOR SYNERGY DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR ClockWorks™ SY10ELT23 ClockWorks™ SY100ELT23 SY10ELT23 SY100ELT23 FEATURES s s s s s s s 3.0ns typical propagation delay <500ps typical output-to-output skew Differential PECL outputs 24mA TTL outputs Flow-through pinouts ESD protection of 2000V Available in 8-pin SOIC package DESCRIPTION The SY10/100ELT23 are dual differential PECL-to-TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT23 makes it ideal for applications which require the tranlation of a clock and a data signal.
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