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Si5384 - Network Synchronizer Clocks Supporting

Download the Si5384 datasheet PDF. This datasheet also covers the Si5383 variant, as both devices belong to the same network synchronizer clocks supporting family and are provided as variant models within a single manufacturer datasheet.

Description

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Features

  • One or three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures.
  • Input frequency range:.
  • External crystal: 25-54 MHz.
  • REF clock: 5-250 MHz.
  • Diff clock: 8 kHz - 750 MHz.
  • LVCMOS clock: 1 PPS, 8 kHz - 250 MHz.
  • Output frequency range:.
  • Differential: 1 PPS, 100 Hz - 718.5 MHz.
  • LVCMOS: 1 PPS, 100 Hz - 250 MHz.
  • Ultra-low jitter of less than 150 fs Si5383/84 IN.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (Si5383-SiliconLaboratories.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Silicon Laboratories

Part Number Description
SI5380 Clock Generator
Si5383 Network Synchronizer Clocks Supporting
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Full PDF Text Transcription

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Si5383/84 Rev D Data Sheet Network Synchronizer Clocks Supporting 1 PPS to 750 MHz Inputs The Si5383/84 combines the industry’s smallest footprint and lowest power network synchronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless communications systems, and data center switches requiring both traditional and packet based network synchronization. The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588 DCO, or a general-purpose PLL for processor/FPGA clocking. The Si5383/84 can also be used in legacy SETS systems needing Stratum 3/3E compliance. In addition, locking to a 1 PPS input frequency is available on DSPLL D.
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