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SLGSSTVF16859V - DDR 13 to 26 Bit Registered Buffer

Download the SLGSSTVF16859V datasheet PDF. This datasheet also covers the SLGSSTVF16859H variant, as both devices belong to the same ddr 13 to 26 bit registered buffer family and are provided as variant models within a single manufacturer datasheet.

General Description

The 14-bit SLGSSTVF16859 is a registered buffer designed for 2.3V to 2.7V VDD operating range.

Inputs are SSTL_2 levels, except for the LVCMOS RESET input.

Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signal (RESET).

Key Features

  • Compatible with JEDEC standard SSTV16859.
  • Differential Clock inputs.
  • SSTL_2 data input signaling.
  • Supports SSTL_2 class I output specifications.
  • Output circuitry minimizes effects of SSO and unterminated lines www. DataSheet4U. com.
  • LVCMOS input levels on RESET pin.
  • 2.3V-2.7V Operation for PC1600/2100/2700.
  • 2.5V-2.7V Operation for PC3200.
  • Max Clock frequency > 210MHz Pin Configuration Q13A Q12A Q11A Q10A Q9A VDDQ G.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SLGSSTVF16859H_Silego.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number SLGSSTVF16859V
Manufacturer Silego
File Size 336.09 KB
Description DDR 13 to 26 Bit Registered Buffer
Datasheet download datasheet SLGSSTVF16859V Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SLGSSTVF16859H/V DDR 13 to 26 Bit Registered Buffer Applications: • PC1600/2100/2700/3200 DDR memory modules • 1:2 Outputs for stacked DDR DIMMS • SSTL_2 compatible data registers Features: • Compatible with JEDEC standard SSTV16859 • Differential Clock inputs • SSTL_2 data input signaling • Supports SSTL_2 class I output specifications • Output circuitry minimizes effects of SSO and unterminated lines www.DataSheet4U.com • LVCMOS input levels on RESET pin • 2.3V-2.7V Operation for PC1600/2100/2700 • 2.5V-2.7V Operation for PC3200 • Max Clock frequency > 210MHz Pin Configuration Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B Block Diagram CLK 48 CLK 49 RESET 51 D1 35 VREF 45 . . ..