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SLGSSTU32864E - DDR2 Configurable Registered Buffer

General Description

The SLGSSTU32864 is a configurable registered buffer designed for 1.7V to 1.9V VDD operating range.

When C1 input pin is low, the SLGSSTU32864 is 1:1 25-bit configuration.

When C1 input pin is high, the SLGSSTU32864 is 1:2 14-bit configuration.

Key Features

  • Compatible with JEDEC standard SSTU32864.
  • Differential Clock inputs.
  • SSTL_18 Clock and data input signaling.
  • Output circuitry minimizes effects of SSO and unterminated lines.
  • LVCMOS input levels on control and RESET pins.
  • 1.7V-1.9V Supply voltage range.
  • Max Clock frequency > 300MHz General.

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Datasheet Details

Part number SLGSSTU32864E
Manufacturer Unknown Manufacturer
File Size 206.94 KB
Description DDR2 Configurable Registered Buffer
Datasheet download datasheet SLGSSTU32864E Datasheet

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SLGSSTU32864E DDR2 Configurable Registered Buffer Features: • Compatible with JEDEC standard SSTU32864 • Differential Clock inputs • SSTL_18 Clock and data input signaling • Output circuitry minimizes effects of SSO and unterminated lines • LVCMOS input levels on control and RESET pins • 1.7V-1.9V Supply voltage range. • Max Clock frequency > 300MHz General Description The SLGSSTU32864 is a configurable registered buffer designed for 1.7V to 1.9V VDD operating range. When C1 input pin is low, the SLGSSTU32864 is 1:1 25-bit configuration. When C1 input pin is high, the SLGSSTU32864 is 1:2 14-bit configuration. Additionally, C0 input pin controls the 1:2 pinout as register-A configuration (if low) , and register-B configuration (if high). The C0,C1, and RESET pins are LVCMOS input levels.