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16 MBit Synchronous DRAM (second generation)
Advanced Information • High Performance: CAS latency = 3 -8 125 8 7 -10 100 10 8 Units MHz ns ns
HYB 39S16400/800/160AT-8/-10
• Multiple Burst Read with Single Write Operation • Automatic and Controlled Precharge Command • Data Mask for Read/Write control (× 4, × 8) • Dual Data Mask for byte control (× 16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • 4096 refresh cycles/64 ms • Random Column Address every CLK (1-N Rule) • Single 3.3 V ± 0.
HYB39S16160AT-10 Datasheet
