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K7R321882M - 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM

General Description

on page 2 and add HSTL I/O comment Draft Date June, 30 2001 Dec.

1.

Update current characteristics in DC electrical characteristics 2.

Key Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future freguency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
  • Separate independent read and write data ports with concurrent read and write operation.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed early write.
  • Registered address, control a.

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Full PDF Text Transcription for K7R321882M (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K7R321882M. For precise diagrams, and layout, please refer to the original PDF.

K7R323682M K7R321882M K7R320982M Document Title 1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM 1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM Revision History Rev. No. 0.0 0.1 H...

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x18-bit, 4Mx9-bit QDRTM II b2 SRAM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. 2. 3. 4. 5. 6. Pin name change from DLL to Doff. Vddq range change from 1.5V to 1.5V~1.8V. Update JTAG test conditions. Reserved pin for high density name change from NC to Vss/SA Delete AC test condition about Clock Input timing Reference Level Delete clock description on page 2 and add HSTL I/O comment Draft Date June, 30 2001 Dec. 5 2001 Remark Advance Preliminary 0.2 1. Update current characteristics in DC electrical characteristics 2. Change AC timing characteristics 3. Update JTAG instruction coding and diagrams 1. 2.

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