Download the K4M51323LC-G datasheet PDF.
This datasheet also covers the K4M51323LC-SN variant, as both devices belong to the same mobile-sdram family and are provided as variant models within a single manufacturer datasheet.
General Description
The K4M51323LC is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology.
Key Features
VDD/VDDQ = 2.5V/2.5V.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the system clock.
Note: The manufacturer provides a single datasheet file (K4M51323LC-SN_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for K4M51323LC-G (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
K4M51323LC-G. For precise diagrams, and layout, please refer to the original PDF.
K4M51323LC - S(D)N/G/L/F 4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • VDD/VDDQ = 2.5V/2.5V • LVCMOS compatible with multiplexed address. • Four banks operation....
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• LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • • • • 64ms refresh period (8K cycle). Commercial Temperature Operation (-25°C ~ 70°C). Extended T
K4M51323LC-G Datasheet
