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STM32MP135D - 32-bit RISC processor

This page provides the datasheet information for the STM32MP135D, a member of the STM32MP135A 32-bit RISC processor family.

Description

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19 3.1 Arm Cortex-A7 subsystem

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Features

  • Includes ST state-of-the-art patented technology Core.
  • 32-bit Arm® Cortex®-A7.
  • L1 32-Kbyte I / 32-Kbyte D.
  • 128-Kbyte unified level 2 cache.
  • Arm® NEON™ and Arm® TrustZone® Memories.
  • External DDR memory up to 1 Gbyte.
  • up to LPDDR2/LPDDR3-1066 16-bit.
  • up to DDR3/DDR3L-1066 16-bit.
  • 168 Kbytes of internal SRAM: 128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain.
  • Dual Quad-SPI memory in.

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Datasheet preview – STM32MP135D

Datasheet Details

Part number STM32MP135D
Manufacturer STMicroelectronics
File Size 2.98 MB
Description 32-bit RISC processor
Datasheet download datasheet STM32MP135D Datasheet
Additional preview pages of the STM32MP135D datasheet.

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Full PDF Text Transcription

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STM32MP135A STM32MP135D Arm® Cortex®-A7 up to 1 GHz, LCD-TFT, camera interface, 2×ETH, 2×CAN FD, 2×ADC, 24 timers, audio Datasheet - production data Features Includes ST state-of-the-art patented technology Core • 32-bit Arm® Cortex®-A7 – L1 32-Kbyte I / 32-Kbyte D – 128-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® Memories • External DDR memory up to 1 Gbyte – up to LPDDR2/LPDDR3-1066 16-bit – up to DDR3/DDR3L-1066 16-bit • 168 Kbytes of internal SRAM: 128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain • Dual Quad-SPI memory interface • Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC Security/safety • TrustZone® peripherals, 12 x tampe
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