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HD74LV166A - Parallel-Load 8-bit Shift Register

Description

The HD74LV166A is 8-bit shift register with an output from the last stage.

Data may be loaded into the register either in parallel or in serial form.

When the Shift/Load input is low, the data is loaded asynchronously in parallel.

Features

  • VCC = 2.0 V to 5.5 V operation.
  • All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V).
  • All outputs VO (Max. ) = 5.5 V (@VCC = 0.

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Datasheet Details

Part number HD74LV166A
Manufacturer Renesas
File Size 98.26 KB
Description Parallel-Load 8-bit Shift Register
Datasheet download datasheet HD74LV166A Datasheet

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Full PDF Text Transcription

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Preliminary Datasheet HD74LV166A Parallel-Load 8-bit Shift Register R04DS0002EJ0400 (Previous: REJ03D0321-0300) Rev.4.00 Aug 16, 2010 Description The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g.
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