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HD74LV166A - Parallel-Load 8-bit Shift Register

Description

The HD74LV166A is 8-bit shift register with an output from the last stage.

Data may be loaded into the register either in parallel or in serial form.

When the Shift/Load input is low, the data is loaded asynchronously in parallel.

Features

  • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max. ) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) HD74LV166A Function Table Inputs CLR L H H H H H SH/LD X X L H H X CLK INH X L L L L H CLK X L ↑ ↑ ↑ ↑ SER X X X H L X.

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Full PDF Text Transcription

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HD74LV166A Parallel-Load 8-bit Shift Register ADE-205-268 (Z) 1st Edition March 1999 Description The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g.
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