HD74CDCV857A Datasheet PDF (2.5-V Phase-lock Loop Clock Driver)

HD74CDCV857A - 2.5-V Phase-lock Loop Clock Driver

Description

The HD74CDCV857A is a high-performance, low-skew, low-jitter, phase locked loop clock driver.

It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.

Features

DDR333 / PC2700-Compliant, also meets DDR266 / PC2100 requirement.
Supports 60 MHz to 170 MHz operation range.
Distributes one differential clock input pair to ten differential clock outputs pairs.
Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM specification.
External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input.
Supports 2.5V analog supply voltage (AVCC), and 2.5 V V.

Datasheet Details

Part number	HD74CDCV857A
Manufacturer	Renesas
File Size	235.33 KB
Description	2.5-V Phase-lock Loop Clock Driver
Datasheet	HD74CDCV857A Datasheet

📁 Similar Datasheet

HD74CDCV857 - 2.5-V Phase-lock Loop Clock Driver (Hitachi Semiconductor)

HD74CDC2509B - 3.3-V Phase-lock Loop Clock Driver (Hitachi Semiconductor)

HD74CDC2510B - 3.3-V Phase-lock Loop Clock Driver (Hitachi Semiconductor)

HD74CDC857 - 3.3/2.5-V Phase-lock Loop Clock Driver (Hitachi Semiconductor)

HD74CDCF2509B - 140 MHz/ 0 to 85C Operation 3.3-V Phase-lock Loop Clock Driver (Hitachi Semiconductor)

HD74CDCF2510B - 140 MHz/ 0 to 85C Operation 3.3-V Phase-lock Loop Clock Driver (Hitachi Semiconductor)

HD74CBT16210 - 20-bit FET Bus Switch (Renesas Technology)

HD74CBT1G125 - Single FET Bus Switch (Renesas Technology)

HD74CBT32160C - 16-bit to 32-bit Demux PCI Hot-plug Bus Switch (Renesas Technology)

HD74CBT3244 - Octal FET Bus Switch (Renesas Technology)

Full PDF Text Transcription

Click to expand full text

HD74CDCV857A 2.5-V Phase-lock Loop Clock Driver REJ03D0136–0300Z (Previous ADE-205-693B (Z)) Rev.3.00 Oct.09.2003 Description The HD74CDCV857A is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs. Features • DDR333 / PC2700-Compliant, also meets DDR266 / PC2100 requirement. • Supports 60 MHz to 170 MHz operation range • Distributes one differential clock input pair to ten differential clock outputs pairs • Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM specification • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input • Supports 2.5V analog supply voltage (AVCC), and 2.

Published: Dec 4, 2017 |