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HD74ALVC2G240 - Dual Bus Buffer Inverted

Description

The HD74ALVC2G240 has dual bus buffer inverted with 3-state output in an 8 pin package.

Output is disabled when the associated output enable (OE) input is high.

Features

  • The basic gate function is lined up as Renesas uni logic series.
  • Supplied on emboss taping for high-speed automatic mounting.
  • Supply voltage range : 1.2 to 3.6 V Operating temperature range:.
  • 40 to +85°C.
  • All inputs VIH (Max. ) = 3.6 V (@VCC = 0 V to 3.6 V) All outputs VO (Max. ) = 3.6 V (@VCC = 0 V).
  • Output current ±2 mA (@VCC = 1.2 V) ±4 mA (@VCC = 1.4 V to 1.6 V) ±6 mA (@VCC = 1.65 V to 1.95 V) ±18 mA (@VCC = 2.3 V to 2.7 V) ±24.

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Other Datasheets by Renesas

Part Number Description
HD74ALVC2G241 Dual Bus Buffer Noninverted
HD74ALVC2G245 Dual Bus Transceivers
HD74ALVC2G00 Dual 2-input NAND Gates
HD74ALVC2G02 Dual 2-input NOR Gates
HD74ALVC2G04 Triple Inverter Buffers

Full PDF Text Transcription

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HD74ALVC2G240 Dual Bus Buffer Inverted with 3-state Output REJ03D0174–0300Z (Previous ADE-205-623B (Z)) Rev.3.00 Dec.18.2003 Description The HD74ALVC2G240 has dual bus buffer inverted with 3-state output in an 8 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series.
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