Datasheet4U Logo Datasheet4U.com

8V49NS0412 - NG Clock Generator

Description

The 8V49NS0412 is a clock generator with four output dividers: three integers, and one that is either integer or fractional.

Features

  • Eleven differential LVPECL and LVDS outputs with programmable voltage swings.
  • One LVCMOS output: Input reference can be passed to this output.
  • The clock input operates in full differential mode (LVDS, LVPECL) or single-ended LVCMOS mode.
  • Driven from a crystal or differential clock input.
  • 2.4.
  • 2.5 GHz PLL frequency range supports Ethernet, SONET, and CPRI frequency plans.
  • Four Integer output dividers with a range of output divide ratios (see Table 5).

📥 Download Datasheet

Datasheet preview – 8V49NS0412

Datasheet Details

Part number 8V49NS0412
Manufacturer Renesas
File Size 1.90 MB
Description NG Clock Generator
Datasheet download datasheet 8V49NS0412 Datasheet
Additional preview pages of the 8V49NS0412 datasheet.

📁 Similar Datasheet

  • 8V49NS0412 - NG Clock Generator (IDT)
  • 8V49NS0312 - Clock Generator (Integrated Device Technology)
  • 8V49N211 - Clock Generator (Integrated Device Technology)
  • 8V41N010 - Clock Generator (Integrated Device Technology)
  • 8V41NS0412 - NG Ultra Low Jitter HCSL Clock Generator (IDT)
  • 8V43FS92432 - 1360MHz Dual Output LVPECL Clock Synthesizer (IDT)
  • 8V44N4614 - NG Jitter Attenuator and Clock Synthesizer (Integrated Device Technology)
  • 8V44S269 - 10-Output Clock Synthesizer (IDT)
Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
FemtoClock® NG Clock Generator with Four Dividers 8V49NS0412 Datasheet Description The 8V49NS0412 is a clock generator with four output dividers: three integers, and one that is either integer or fractional. When used with an external crystal, the 8V49NS0412 generates high-performance timing for the communications and datacom markets, especially for applications that demand extremely low phase noise, such as 10GE, 40GE, 100G, and 400GE. The 8V49NS0412 provides versatile frequency configurations and output formats, and is optimized to deliver excellent phase noise performance. The device delivers an optimum combination of high clock frequency and low phase noise performance, combined with high power supply noise rejection.
Published: |