8V44N4614 Datasheet PDF (NG Jitter Attenuator and Clock Synthesizer) | Download Integrated Device Technology 8V44N4614

8V44N4614 - NG Jitter Attenuator and Clock Synthesizer

Description

The 8V44N4614 is a FemtoClock® NG Clock Generator.

The device has been designed for frequency generation in high-performance systems such wireless base-band boards, for instance to drive the reference clock inputs of processors, PHY, switch and SerDes devices.

Features

Clock generator for wireless base-band systems.
Drives reference clock inputs of processors, PHY, switch and SerDes devices.
FemtoClock® NG technology.
Three low-skew, differential LVDS, LVPECL configurable clock outputs.
Ten low-skew, LVCMOS/LVTTL clock outputs.
Input: 200MHz, 100MHz, 50MHz, 25MHz single-ended (LVCMOS) or differential reference clock (LVDS, LVPECL).
Output clocks support 156.25MHz, 125MHz, 100MHz and 25MHz.

Datasheet Details

Part number	8V44N4614
Manufacturer	Integrated Device Technology
File Size	593.68 KB
Description	NG Jitter Attenuator and Clock Synthesizer
Datasheet	8V44N4614 Datasheet
Additional preview pages of the 8V44N4614 datasheet.

📁 Similar Datasheet

8V44S269 - 10-Output Clock Synthesizer (IDT)

8V41N012A - Clock Generator (Renesas)

8V41NS0412 - NG Ultra Low Jitter HCSL Clock Generator (Renesas)

8V41NS0412 - NG Ultra Low Jitter HCSL Clock Generator (IDT)

8V43FS92432 - 1360MHz Dual Output LVPECL Clock Synthesizer (IDT)

8V49N211 - Clock Generator (Renesas)

8V49NS0312 - NG Clock Generator (Renesas)

8V49NS0412 - NG Clock Generator (IDT)

8V49NS0412 - NG Clock Generator (Renesas)

Full PDF Text Transcription

Click to expand full text

FemtoClock® NG Jitter Attenuator and  Clock Synthesizer 8V44N4614 DATA SHEET General Description The 8V44N4614 is a FemtoClock® NG Clock Generator. The device has been designed for frequency generation in high-performance systems such wireless base-band boards, for instance to drive the reference clock inputs of processors, PHY, switch and SerDes devices. The device is very flexible in frequency programming. It allows to generate the clock frequencies of 156.25MHz, 125MHz, 100MHz and 25MHz individually at three output banks. One output bank supports configurable LVDS, LVPECL, the other two output banks support LVCMOS output levels. All outputs are synchronized on the incident rising edge, regardless of the selected output frequency.

Published: Mar 5, 2016 |