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HYI25D512160C - 512-Mbit Double-Data-Rate SDRAM

Description

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an Active command, which is then followed by a Read or Write command.

Features

  • es Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask re.

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Datasheet Details

Part number HYI25D512160C
Manufacturer Qimonda
File Size 1.85 MB
Description 512-Mbit Double-Data-Rate SDRAM
Datasheet download datasheet HYI25D512160C Datasheet

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Full PDF Text Transcription

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November 2006 HYI25D512160C[C/E/F/T] www.DataSheet4U.com 5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M DDR SDRAM Internet Data Sheet Rev. 1.0 Internet Data Sheet HYI25D512160C[C/E/F/T] 512-Mbit Double-Data-Rate SDRAM HYI25D512160C[C/E/F/T] Revision History: 2006-11, Rev. 1.0 Page www.DataSheet4U.com Subjects (major changes since last revision) Adapted internet edition Qimonda update, first final revision All All We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.
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