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HYI25D256160C - 256-Mbit Double-Data-Rate SDRAM

Description

DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Features

  • Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP = tRCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 compatible) I/O VDDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400) VDD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDD = 2.6 V ± 0.1 V (DDR400) Standard Temperature Range (0 °C - +70 °C) or.

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Datasheet Details

Part number HYI25D256160C
Manufacturer Qimonda
File Size 2.11 MB
Description 256-Mbit Double-Data-Rate SDRAM
Datasheet download datasheet HYI25D256160C Datasheet

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Full PDF Text Transcription

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March 2007 HYB25D256[40/80/16]0CE(L) HYB25D256[40/80/16]0C[T/C/F] HYI25D256[80/16]0C[C/E/F/T] www.DataSheet4U.com 256-Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant or Lead-Containing Internet Data Sheet Rev. 2.3 Internet Data Sheet HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM HYB25D256[40/80/16]0CE(L), HYB25D256[40/80/16]0C[T/C/F], HYI25D256[80/16]0C[C/E/F/T] Revision History: 2007-03, Rev. 2.3 Page All 17 www.DataSheet4U.com 72 85, 86 Subjects (major changes since last revision) Adapted internet edition Corrected table 7 mode register definition Changed the 1.1 mA to 1.5 mA for low power Changed the ball size from 0.460 mm to 0.450 mm Previous Revision: 2007-01, Rev. 2.
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