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MC74VHC125 - Quad Bus Buffer

Key Features

  • High Speed: tPD = 3.8 ns (Typ) at VCC = 5 V.
  • Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C.
  • High Noise Immunity: VNIH = VNIL = 28% VCC.
  • Power Down Protection Provided on Inputs.
  • Balanced Propagation Delays.
  • Designed for 2 V to 5.5 V Operating Range.
  • Low Noise: VOLP = 0.8 V (Max).
  • Pin and Function Compatible with Other Standard Logic Families.
  • Latchup Performance Exceeds 100 mA.
  • ESD Performance: Huma.

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Full PDF Text Transcription for MC74VHC125 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for MC74VHC125. For precise diagrams, and layout, please refer to the original PDF.

DATA SHEET www.onsemi.com Quad Bus Buffer with 3-State Control Inputs MC74VHC125, MC74VHCT125A The MC74VHC125 and MC74VHCT125A are high speed CMOS bus buffers fabricated ...

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C74VHC125 and MC74VHCT125A are high speed CMOS bus buffers fabricated with silicon gate CMOS technology. These achieve high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. These devices require the 3−state control input (OE) to be set High to place the output into the high impedance state. The MC74VHC125 inputs are compatible with standard CMOS levels while the MC74VHCT125A inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings.

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