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SM8213AM - POCSAG Decoder

Description

Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1.

I O O I O I O I O RF control main output signal RF DC-level adjustment signal PLL setup signal NRZ signal inpu

Features

  • a built-in filter. Each of the addresses (max. 7 + 1 dummy = 8) can be assigned to any frame, which also makes the device configurable for many additional services. Each address can be independently set to ON/OFF. Furthermore, built-in buffer memory means decoded information can be fetched in sync with the microcontroller clock, thereby reducing the microcontroller CPU time required. Intermittent-duty method (battery saving (BS) method) control signals, compatible with PLL operation, and Molybdenu.

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Datasheet preview – SM8213AM

Datasheet Details

Part number SM8213AM
Manufacturer Nippon Precision Circuits Inc
File Size 171.79 KB
Description POCSAG Decoder
Datasheet download datasheet SM8213AM Datasheet
Additional preview pages of the SM8213AM datasheet.

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Full PDF Text Transcription

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SM8213AM NIPPON PRECISION CIRCUITS INC. POCSAG Decoder For Multiframe Pagers OVERVIEW The SM8213AM is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes. The SM8213AM supports call messages in either tone, numerical or character outputs at signal speeds of 512, 1200 or 2400 bps. The signal input stage features a built-in filter. Each of the addresses (max. 7 + 1 dummy = 8) can be assigned to any frame, which also makes the device configurable for many additional services. Each address can be independently set to ON/OFF.
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