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SM8212B - POCSAG Decoder

Description

Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name BS1 BS2 BS3 SIGNAL XVSS XT XTN VSS CLKO RSTN AREA SCK SDO SDI ATTN VDD i/o o o o i i o o i o i o i o Description RF control main output signal RF DC-level adjustment signal PLL setup signal NRZ signal input pin Crystal oscillator ground.

Features

  • a built-in filter. Each of the addresses (max. 8) can be assigned to any frame, which also makes the device configurable for many additional services. Each address can be independently set ON/OFF. Furthermore, built-in buffer memory means decoded information can be fetched in sync with the microcontroller clock, thereby reducing the microcontroller CPU time required. Intermittent-duty method (battery saving (BS) method) control signals, compatible with PLL operation, and Molybdenum-gate CMOS str.

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Datasheet preview – SM8212B

Datasheet Details

Part number SM8212B
Manufacturer Nippon Precision Circuits Inc
File Size 167.00 KB
Description POCSAG Decoder
Datasheet download datasheet SM8212B Datasheet
Additional preview pages of the SM8212B datasheet.

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Full PDF Text Transcription

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SM8212B NIPPON PRECISION CIRCUITS INC. POCSAG Decoder For Multiframe Pagers - BS2 (RF DC-level adjustment signal) before/during reception selectable adjustment timing - 1-bit and 2-bit burst error auto-correction function - 25 to 75% duty factor signal coverage - 8 rate error detection condition settings - 76.8 kHz system clock (crystal oscillator) - 76.8 or 38.4 kHz clock output pin - Built-in oscillator capacitor and feedback resistor - 2.0 to 3.5 V operating supply voltage - Molybdenum-gate CMOS process realizes low power dissipation - 16-pin SSOP OVERVIEW The SM8212B is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes.
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